1. Field of the Invention
This invention relates to the programming of memory cells in an array of split gate flash memory cells, and more particularly to avoiding program disturb during the programming cycle thereby allowing smaller cell sizes.
2. Description of the Related Art
Electrically alterable read only memory cells, or EEPROM memory cells, which can be electronically programmed and erased find frequent use in memory arrays. Flash memories having either a split gate or a stacked gate structure are often used for this purpose. During the programming cycle of these memory arrays it is important that cells which are not selected for the programming cycle are not disturbed by the programming of the selected cell. Avoiding this program disturb problem can place dimensional requirements on the design of the individual memory cells.
U.S. patent application Ser. No. 09/298,142 (TSMC-98-258), filed on Apr. 23, 1999, entitled "SOURCE SIDE INJECTION PROGRAMMING AND TIP ERASING P-CHANNEL SPLIT GATE FLASH MEMORY CELL", and assigned to the same Assignee describes a method of forming a P channel split gate flash memory cell.
U.S. Pat. No. 5,067,108 to Jenq describes a split gate flash memory cell using hot electron injection into the floating gate to program the cell and Fowler-Nordheim tunneling of electrons from the floating gate to the control gate to erase the cell.
U.S. Pat. No. 5,579,261 to Radjy et al. describes a method of programming a cell in an array of stacked gate flash memory cells in order to reduce leakage current during programming. The invention of Radjy et al. describes only stacked gate cells and not split gate cells.
U.S. Pat. No. 5,600,592 to Astumi et al. describes a flash memory EEPROM device having a word line with a negative voltage applied. A stacked gate flash memory cell is used in the memory. The invention of Astumi describes only stacked gate cells and not split gate cells.
U.S. Pat. No. 5,408,429 to Sawada describes a method for writing data to a selected EEPROM memory cell and erasing data in a selected EEPROM memory cell. The invention of Sawada describes only stacked gate flash memory cells.
U.S. Pat. No. 5,416,738 to Shrivastava describes a single transistor flash memory cell. The invention of Shrivastava describes only stacked gate flash memory cells.